cmos area image sensors aps (active pixel sensor) type with high near infrared sensitivity s11661 s11662 www.hamamatsu.com 1 the s11661 and s11662 are aps type cmos area image sensors with a high sensitivity in the near infrared region. the s11661 is sxga format type (1280 x 1024 pixels), and the s11662 is vga format type (640 x 480 pixels). both types include a timing generator, a bias generator and an a/d converter, and offer digital input/output for easy handling. pixel size: 7.4 7.4 m 3.3 v single power supply operation rolling/global shutter readout high-speed partial readout function s11661: 1280 1024 pixels s11662: 640 480 pixels security (infrared camera, palm vein certi cation) position and shape recognition of infrared spot light features applications absolute maximum ratings structure parameter symbol condition value unit supply voltage vdd(a), vdd(d) ta=25 c -0.3 to +4.2 v input voltage * 3 vi ta=25 c -0.3 to +4.2 v vcp_out terminal voltage vcp_out ta=25 c -0.3 to +6.5 v operating temperature * 4 topr -10 to +65 c storage temperature * 4 tstg -10 to +85 c re ow soldering conditions * 5 tsol peak temperature 260 c, 3 times (see p.8) - * 3: spi_data, spi_clk, spi_enable, mclk, vref1 to 9, vr, vcp_in, all_reset, mst, spi_reset * 4: no dew condensation when there is a temperature difference between a product and the surrounding area in high humidity environment, dew condensatio n may occur on the product surface. dew condensation on the product may cause deterioration in characteristics and reliability. * 5: jedec level 3 (s11661), jedec level 2a (s11662) note: exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. always be sure to use the product within the absolute maximum ratings. parameter s11661 s11662 unit image size (h v) 9.472 7.578 4.736 3.552 mm pixel size 7.4 7.4 m pixel pitch 7.4 m number of total pixels (h v) 1320 1064 680 520 pixels number of effective pixels (h v) 1280 1024 640 480 pixels number of light-shielded lines upper and left parts: 8 each lower and right parts: 32 each lines fill factor 33 % package ceramic - window material * 1 * 2 borosilicate glass (without anti-re ective coating) - * 1: resin sealing * 2: re active index=1.523
cmos area image sensors s11661, s11662 2 recommended terminal voltage (ta=25 c) electrical characterisitics [ta=25 c, vdd(a)=vdd(d)=3.3 v] parameter symbol min. typ. max. unit supply voltage vdd(a), vr 3.0 3.3 3.6 v i/o supply voltage vdd(d), vcp_in 3.0 vdd(a) 3.6 v digital input terminal voltage high level vsigi(h) vdd(d) - 0.25 vdd(d) vdd(d) + 0.25 v low level vsigi(l) 0 - 0.4 parameter symbol min. typ. max. unit master clock pulse frequency f(mclk) 1 m - 25 m hz video data rate vr 1/2 f(mclk) hz digital output voltage high level vsigo(h) vdd(d) - 0.25 vdd(d) - v low level vsigo(l) - 0 0.25 current consumption* 6 analog terminal * 7 i1 - 47 55 ma digital terminal * 8 i2 - 25 (s11661) 19 (s11662) 45 (s11661) 35 (s11662) * 6: master clock pulse frequency: 25 mhz, frame rate: 8 frames/s (s11661), 30 frames/s (s11662), load capacitance of each output terminal: 5 pf *7: sum of vdd(a) and vr terminals *8: sum of vdd(d) and vcp_in terminals electrical and optical characterisitics [ta=25 c, vdd(a)=vdd(d)=3.3 v, gain=1 times] parameter symbol min. typ. max. unit spectral response range 400 to 1000 nm peak sensitivity wavelength p - 760 - nm photosensitivity * 9 sw 10 13 - v/lx?s photoresponse nonuniformity * 10 prnu - - 4 % dark output* 11 * 12 vdark - 60 180 mv/s saturation output voltage vsat 1.4 1.6 - v saturation exposure lsat 0.1 0.12 - lx?s linearity lr - - 10 % image lag lag - - 0.1 % random noise * 12 rolling shutter mode rn(rs) - 1000 1500 v rms global shutter mode rn(gs) - 1500 2250 v rms dynamic range rolling shutter mode dr(rs) 59 64 - db global shutter mode dr(gs) 55 60 - db blemish point defect * 13 white spots ws - - 10 pixels black spots bs - - 10 pixels cluster defect * 14 clsd - - 0 pieces line defect * 15 dl - - 0 lines * 9: white light 2856 k * 10: photoresponse nonuniformity (prnu) is the output nonuniformity that occurs when the photosensitive area is uniformly illuminate d by white light which is approx. 50% of the saturation level. prnu is calculated using the pixels excluding the pixels of the 10 outermost lines and defective pixels, and is de ned as follows: prnu= ? x/x 100 (%) x: average output of all pixels, ? x: standard deviation of pixel output * 11: average value of all effective pixels (excluding defective pixels). rolling shutter mode * 12: analog video output value the nal output from the image sensor is a 12-bit digital signal. when the gain is set to 1, the conversion voltage range (0 to 2 v ) is a/d converted into 4096 gradation steps. so, 1 dn (digital number) is equal to 0.488 mv (=2000 mv/4096 dn). * 13: white spot=pixels whose dark output exceeds 1800 mv/s black spot= pixels whose sensitivity is less than 50% of the average sensitivity of adjacent pixels when the image sensor is illuminated with uniform white light that is approximately 50% of the saturation (excluding the outermost 10 lines in the effective pixel area) * 14: a defect consisting of two or more contiguous defective pixels * 15: column defect and row defect column defect=a defect consisting of 10 or more contiguous defective pixels in one column row defect=a defect consisting of 10 or more contiguous defective pixels in one row
cmos area image sensors s11661, s11662 3 spectral response (typical example) contrast transfer function vs. spatial frequency (typical example) spectral transmittance characteristics of window material 0 400 500 600 700 900800 1000 1100 1200 25 20 15 10 5 (ta=25 c) photosensitivity [tv/(w?s)] wavelength (nm) transmittance (%) wavelength (nm) 100 (typ. ta=25 c) 80 60 40 20 0 200 300 400 500 600 700 800 900 1000 1100 1200 kmpdb0363ec kmpdb0423ea electrical and optical characterisitics [a/d converter, ta=25 c, vdd(a)=vdd(d)=3.3 v] parameter symbol value unit resolution reso 12 bits conversion time tcon 2/f(mclk) s conversion voltage range * 16 - 0 to 2 v *16: gain=1 0 0 5 10 20 15 25 1.0 0.8 0.6 0.4 0.2 (white light, ta=25 c) contrast transfer function spatial frequency (line pairs/mm) kmpdb0424ea
cmos area image sensors s11661, s11662 4 block diagram s11661: 1280 1024 pixels s11662: 640 480 pixels ( ) photodiode array vertical shift register (s11661: 1064 lines, s11662: 520 lines) booster circuit timing generator horizontal shift register (s11661: 1320 lines, s11662: 680 lines) cds circuit (s11661: 1320 lines, s11662: 680 lines) serial/parallel interface mclk all_reset (mst) spi_reset spi_data spi_clk spi_enable amplifier bias circuit 12-bit a/d converter vsync dout [11-0] hsync pclk 12 kmpdc0409ea s11661 angle accuracy of effective pixels: 2.4 weight: 1.4 g * 1: distance from upper surface of window to photosensitive surface * 2: distance from package bottom to photosensitive surface 9.472 center of photosensitive area 23 33 33 23 1 11 11 1 34 44 22 12 22 12 34 44 16.0 0.1 1.27 16.51 +0.30 -0.18 7.578 photosensitive surface 0.9 0.2 * 2 1.4 0.14 7.49 0.2 7.96 0.2 scan direction (vertical) scan direction (horizontal) 1 ch 1.05 0.2* 1 12.7 0.13 1.27 0.13 0.635 0.13 0.55 0.05 index mark dimensional outlines (unit: mm) kmpda0286ec
cmos area image sensors s11661, s11662 5 25 36 12 1 37 48 24 13 10.2 0.1 10.67 +0.20 -0.13 4.736 0.9 0.2 * 2 1.05 0.2 * 1 0.55 0.05 1.4 0.14 36 25 1 12 37 48 24 13 0.7 5.16 0.2 4.22 0.2 *1: distance from upper surface of window to photosensitive surface *2: distance from package bottom to photosensitive surface angle accuracy of effective pixels: 3.15 weight: 0.5 g photosensitive surface scan direction (vertical) scan direction (horizontal) center of photosensitive area index mark 0.4 0.05 1 ch 7.7 0.1 0.8 0.18 3.552 s11662 kmpda0287eb s11661 s11662 12.7 1.27 16.24 2.27 0.65 7.7 0.7 10.67 0.4 2.0 kmpdc0527ea kmpdc0528ea land pattern examples (unit: mm)
cmos area image sensors s11661, s11662 6 s11661 pin no. symbol description i/o 1 gnd ground i 2 spi_data data signal for serial/parallel interface i 3 spi_clk clock signal for serial/parallel interface i 4 spi_enable enable signal for serial/parallel interface i 5 mclk master clock signal i 6 vdd(a) supply voltage (3.3 v) i 7 dout11 video output signal (msb) o 8 dout10 video output signal o 9 dout9 video output signal o 10 dout8 video output signal o 11 dout7 video output signal o 12 vdd(d) supply voltage (3.3 v) i 13 dout6 video output signal o 14 dout5 video output signal o 15 dout4 video output signal o 16 dout3 video output signal o 17 dout2 video output signal o 18 dout1 video output signal o 19 dout0 video output signal (lsb) o 20 vref1 bias voltage for a/d converter * 17 i 21 vref2 bias voltage for a/d converter * 17 i 22 vref3 bias voltage for a/d converter * 17 i 23 vref4 bias voltage for a/d converter * 17 i 24 vref5 bias voltage for a/d converter * 17 i 25 vr supply voltage (3.3 v) * 18 * 19 i 26 gnd ground i 27 vcp_in supply voltage (3.3 v) * 18 * 20 i 28 vdd(a) supply voltage (3.3 v) i 29 vcp_out bias voltage for booster circuit * 21 i 30 vr supply voltage (3.3 v) * 18 * 19 i 31 vref6 bias voltage for cds circuit * 17 i 32 nc no connection - 33 vref7 bias voltage for cds circuit * 17 i 34 vref8 bias voltage for ampli er* 17 i 35 vref9 bias voltage for ampli er* 17 i 36 all_reset all reset pulse signal i 37 mst master start signal i 38 pclk pixel output synchronization signal o 39 hsync line synchronization signal o 40 vsync frame synchronization signal o 41 vdd(d) supply voltage (3.3 v) i 42 vdd(a) supply voltage (3.3 v) i 43 nc no connection - 44 spi_reset reset signal for serial/parallel interface i * 17: terminal for monitoring the bias voltage generated in the chip. to reduce noise, insert a capacitor of about 1 f between the ground and each terminal. * 18: to reduce noise, insert a capacitor of about 0.1 f and an electrolytic capacitor of about 22 f/25 v between the ground and each terminal. * 19: connect this terminal to vdd(a). * 20: connect this terminal to vdd(d). * 21: voltage of approx. 5.5 v, which was boosted by the chip's internal booster circuit, appears at the terminal. to maintain th e voltage, insert a capacitor of about 1 f between the ground and vcp_out. pin connections
cmos area image sensors s11661, s11662 7 s11662 pin no. symbol description i/o 1 spi_enable enable signal for serial/parallel interface i 2 nc no connection - 3 dout11 video output signal (msb) o 4 dout10 video output signal o 5 dout9 video output signal o 6 dout8 video output signal o 7 dout7 video output signal o 8 dout6 video output signal o 9 dout5 video output signal o 10 dout4 video output signal o 11 dout3 video output signal o 12 vdd(d) supply voltage (3.3 v) i 13 vdd(a) supply voltage (3.3 v) i 14 dout2 video output signal o 15 dout1 video output signal o 16 dout0 video output signal (lsb) o 17 vref1 bias voltage for a/d converter * 22 i 18 vref2 bias voltage for a/d converter * 22 i 19 vref3 bias voltage for a/d converter * 22 i 20 vref4 bias voltage for a/d converter * 22 i 21 vref5 bias voltage for a/d converter * 22 i 22 gnd ground i 23 vref6 bias voltage for cds circuit * 22 i 24 vref7 bias voltage for cds circuit * 22 i 25 vref8 bias voltage for ampli er * 22 i 26 nc no connection - 27 vcp_in supply voltage (3.3 v) * 23 * 24 i 28 vr supply voltage (3.3 v) * 23 * 25 i 29 nc no connection - 30 nc no connection - 31 nc no connection - 32 nc no connection - 33 gnd ground i 34 vr supply voltage (3.3 v) * 23 * 25 i 35 vcp_out bias voltage for booster circuit * 26 i 36 all_reset all reset pulse signal i 37 mclk master clock signal i 38 mst master start signal i 39 pclk pixel output synchronization signal o 40 hsync line synchronization signal o 41 vsync frame synchronization signal o 42 vref9 bias voltage for ampli er* 22 i 43 vdd(a) supply voltage (3.3 v) i 44 vdd(d) supply voltage (3.3 v) i 45 gnd ground i 46 spi_reset reset signal for serial/parallel interface i 47 spi_data data signal for serial/parallel interface i 48 spi_clk clock signal for serial/parallel interface i * 22: terminal for monitoring the bias voltage generated in the chip. to reduce noise, insert a capacitor of about 1 f between the ground and each terminal. * 23: to reduce noise, insert a capacitor of about 0.1 f and an electrolytic capacitor of about 22 f/25 v between the ground and each terminal. * 24: connect the terminal to vdd(d). * 25: connect the terminal to vdd(a). * 26: voltage of approx. 5.5 v, which was boosted by the chip's internal booster circuit, appears at the terminal. to maintain th e voltage, insert a capacitor of about 1 f between the ground and vcp_out.
cmos area image sensors s11661, s11662 8 precautions (1) electrostatic countermeasures this device has a built-in protection circuit against static electrical char ges. however, to prevent destroying the device with electro- static charges, take countermeasures such as grounding yourself, the workbench and tools to prevent static discharges. also protect this device from surge voltages which might be caused by peripheral equipment. (2) incident window if dust or dirt gets on the light incident window, it will show up as black blemishes on the image. when cleaning, avoid rubbin g the window surface with dry cloth or dry cotton swab, since doing so may generate static electricity. use soft cloth, paper or a co tton swab moistened with alcohol to wipe dust and dirt off the window surface. then blow compressed air onto the window surface so that no spot or stain remains. (3) soldering by hand to prevent damaging the device during soldering, take precautions to prevent excessive soldering temperatures and times. soldering should be performed within 5 seconds at a soldering temperature below 260 c. (4) re ow soldering soldering conditions may differ depending on the board size, re ow furnace, etc. check the conditions before soldering. a sudden temperature rise and cooling may be the cause of trouble, so make sure that the temperature change is within 4 c per second. the bonding portion between the ceramic base and the glass may discolor after re ow soldering, but this has no adverse effects on the hermetic sealing of the product. (5) uv exposure this product is not designed to prevent deterioration of characteristics caused by uv exposure, so do not expose it to uv light . time 300 c preheating 60 to 120 s soldering 60 to 150 s peak temperature 260 c max. 217 c 200 c 150 c peak temperature - 5 c 30 s max. 25 c to peak temperature 8 m max. heating 3 c/s max. cooling 6 c/s max. temperature kmpdb0405ea recommended temperature pro le for re ow soldering (typical example) recommended baking conditions ? this product supports lead-free soldering. after unpacking, store it in an environment at a temperature of 30 c or less and a humidity of 60% or less, and perform soldering within 168 hours (s11661) or 4 weeks (s11662). ? the effect that the product receives during re ow soldering varies depending on the circuit board and re ow oven that are used. before actual re ow soldering, check for any problems by tesitng out the re ow soldering methods in advance. refer to the precautions of ? surface mount type products.?
cat. no. kmpd1133e03 oct. 2015 dn www.hamamatsu.com hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184 u.s.a.: hamamatsu corporation: 360 foothill road, bridgewater, n.j. 08807, u.s.a., telephone: (1) 908-231-0960, fax: (1) 908-23 1-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 8152-375-0, fax: (49) 8152-265-8 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, telephone: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, united kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: torshamnsgatan 35 16440 kista, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-5 09-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1 int. 6, 20020 arese (milano), italy, telephone: (39) 02-93581733 , fax: (39) 02-93581741 china: hamamatsu photonics (china) co., ltd.: b1201, jiaming center, no.27 dongsanhuan beilu, chaoyang district, beijing 100020 , china, telephone: (86) 10-6586-6006, fax: (86) 10-6586-2866 product specifications are subject to change without prior notice due to improvements or other reasons. this document has been carefully prepared and the information contained is believed to be accurate. in rare cases, however, there may be inaccuracies such as text errors. before using these products, always contact us for the delivery specification sheet to check the latest specifications. the product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. however, even if within the warranty period we accept absolutely no liability for any loss caused by natural d isasters or improper product use. copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. information described in this material is current as of october, 2015. cmos area image sensors s11661, s11662 9 related information precautions ? disclaimer ? image sensors ? surface mount type products www.hamamatsu.com/sp/ssd/doc_en.html hamamatsu provides technical information of this product. please contact our sales of ce.
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